parallel register
英 [ˈpærəlel ˈredʒɪstə(r)]
美 [ˈpærəlel ˈredʒɪstər]
平行寄存器，并行寄存器
双语例句
- For communication among parallel print port of PC and multiple single-chips, interface is divided into data, state and control groups respectively controlled by each register.
PC并行打印口与多台下位单片机的通讯，将接口分成数据、状态、控制三组，由其寄存器分别控制。 - Taking the characteristics of the three registers into account, we use the data register of the parallel interface to transmit data, the state register to receive data and synchronize clock and the control register to control the transceiver's PTT in this paper.
针对这3个寄存器特点，采用计算机并行接口数据寄存器发送数据，状态寄存器接收数据和同步时钟，控制寄存器控制电台PTT。 - Based on the properties of Enhanced Parallel Port ( EPP), an interface of shift register output has been developed using Complex Programmable Logic Device ( CPLD).
基于EPP协议的特点，应用复杂可编程逻辑器件（CPLD）开发了移位寄存器输出接口。 - Multiplexers are adopted to accelerate the left shift operation, and parallel processing based on data dependency is used to optimize RTL ( Register Transfer Language) code to shorten the main critical path.
引入多路选择器来加速实现任意位左移，在提高主关键路径并行性的同时，采用了多种方法对寄存器传输级代码进行优化。 - The synchronous data transmission system terminal of a transceiver always transmits bit by bit transparently when receiving and transmitting data. A computer parallel interface includes three ports respectively for a data register, a state register and a control register.
电台同步数据传输系统终端在收发数据时一般为透明逐bit传输，计算机并行接口包括数据寄存器、状态寄存器和控制寄存器3个端口。 - Based on the jointed test action group ( JTAG) protocol, instructions and scan chain were introduced. With test access port ( TAP) module exchanging serial input with parallel output, register files and random access memory on chip were read or written in parallel.
在JTAG接口协议的基础上，增加指令和扫描链，同时通过测试访问端（TAP）控制把串行输入转换成并行输出，并行访问数字信号处理器的寄存器文件和片上存储器单元，实现嵌入式模拟器。 - Design the Viterbi decoder in VHDL language, employ eight-voltage quantum soft decision and parallel structure, improve the decode speed, present information storage and management to ameliorate the traditional register exchange method.
采用VHDL语言设计了Viterbi译码器，采用八电平量化软判决和并行结构，提高了译码速度，引入信息存储和管理对传统的寄存器交换法进行改进。 - The main structure of the hardware including top timing control unit, bram and its timing generator, serial to parallel converter, shift register, multiplexer, processing element and multi-level adders.
硬件结构主要包括总体时序控制单元、存储单元及其时序发生器、串并转换单元、移位器、选通器、运算单元和级联加法器。